Call for papers

Artificial intelligence is progressing ever faster with new applications and results that would not be possible only a few years ago. At the same time, hardware security is becoming increasingly important for embedded systems applications where the number of such applications keeps on growing. The connection between AI and hardware security is becoming more prominent. Today, there are numerous applications where AI has either an offensive or defensive role for HW security. AIHWS aims to position itself in the intersection of these topics and provide a space where ideas converge into exciting new approaches for HW security. This workshop will provide an environment for researchers from academic and industrial domains to discuss findings and on-going work on all aspects of hardware security and artificial intelligence including design, attacks, manufacturing, testing, validation, utilization.

Topics of the workshop

  • Side-channel attacks and countermeasures

  • Trustworthy manufacturing and testing of secure devices

  • Validation and evaluation methodologies for physical security

  • Reconfigurable devices for security

  • Hardware Trojans

  • Fault injection attacks

  • Physical Unclonable Function (PUFs)

Registration

We encourage researchers working on all aspects of AI and HW security to take the opportunity and use AIHWS to share their work and participate in discussions. The authors are invited to submit the papers using EasyChair submission system.
Every accepted paper must have at least one author registered for the workshop. All submissions must follow the original LNCS format with a page limit of 18 pages, including references and possible appendices. Papers should be submitted electronically in PDF format.

Important dates

Deadlines extended

Workshop paper submission deadline: July 5, 2020

Workshop paper notification: Aug 5, 2020

Camera-ready papers for pre-proceedings: Aug 19, 2020

Workshop dates: October 19-22, 2020

(in parallel with the main conference)

Program (TBA)

Organizing Committee

Technical Program Committee

Shivam Bhasin, Nanyang Technological University, Singapore

Carlos Castro, UCM, Spain

Lukasz Chmielewski, Radboud University, and Riscure, The Netherlands

Chitchanok Chuengsatiansup, The University of Adelaide, Australia

Joan Daemen, Radboud University, The Netherlands

Fatemeh Ganji, University of Florida, United States

Julio Hernandez-Castro, University of Kent, UK

Annelie Heuser, CNRS/IRISA, France

Dirmanto Jap, Nanyang Technological University, Singapore

Alan Jović, University of Zagreb, Croatia

Liran Lerman, Thales, Belgium

Luca Mariot, TU Delft, The Netherlands

Nele Mentens, KU Leuven, Belgium

Kostas Papagiannopoulos, NXP, Germany

Guilherme Perin, TU Delft, The Netherlands

Lex Schoonen, Brightsight, The Netherlands

Shahin Tajik, University of Florida, United States

Vincent Verneuil, NXP, Germany

Nikita Veshchikov, NXP, Belgium

Jason Xue, The University of Adelaide, Australia

Web Chair

Marina Krček, TU Delft, The Netherlands

Questions about the workshop?
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